Invention Grant
US07676777B2 Method and apparatus for supporting verification, and computer product
失效
支持验证的方法和装置,以及计算机产品
- Patent Title: Method and apparatus for supporting verification, and computer product
- Patent Title (中): 支持验证的方法和装置,以及计算机产品
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Application No.: US11727623Application Date: 2007-03-27
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Publication No.: US07676777B2Publication Date: 2010-03-09
- Inventor: Satoshi Kowatari , Yoshiro Nakamura , Takako Shindo
- Applicant: Satoshi Kowatari , Yoshiro Nakamura , Takako Shindo
- Applicant Address: JP Tokyo
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Tokyo
- Agency: Staas & Halsey LLP
- Priority: JP2006-088794 20060328
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F19/00

Abstract:
A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.
Public/Granted literature
- US20070234249A1 Method and apparatus for supporting verification, and computer product Public/Granted day:2007-10-04
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