Invention Grant
- Patent Title: Techniques for super fast buffer insertion
- Patent Title (中): 超快速缓冲插入技术
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Application No.: US11947706Application Date: 2007-11-29
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Publication No.: US07676780B2Publication Date: 2010-03-09
- Inventor: Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
- Applicant: Charles Jay Alpert , Zhuo Li , Stephen Thomas Quay
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Libby Z. Handelsman; Jack V. Musgrove
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.
Public/Granted literature
- US20080072202A1 TECHNIQUES FOR SUPER FAST BUFFER INSERTION Public/Granted day:2008-03-20
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