Invention Grant
US07678411B2 Method of forming wiring pattern and method of forming gate electrode for TFT
有权
形成布线图案的方法和形成TFT的栅电极的方法
- Patent Title: Method of forming wiring pattern and method of forming gate electrode for TFT
- Patent Title (中): 形成布线图案的方法和形成TFT的栅电极的方法
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Application No.: US11206802Application Date: 2005-08-19
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Publication No.: US07678411B2Publication Date: 2010-03-16
- Inventor: Toshimitsu Hirai , Shinri Sakai
- Applicant: Toshimitsu Hirai , Shinri Sakai
- Applicant Address: JP Toyko
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Toyko
- Agency: Oliff & Berridge, PLC
- Priority: JP2004-247908 20040827
- Main IPC: B05D5/12
- IPC: B05D5/12

Abstract:
The invention provides a method of forming a wiring pattern in which a conductive material layer is formed in a pattern formation region having a first region, which is bordered by a bank pattern and has a first width, and a second region, which touches the first region and has a second width smaller than the first width, on a substrate, by discharging a droplet of a conductive material in a liquid phase using a droplet discharge device. The method includes forming the conductive material layer to cover the first region and the second region, by discharging the droplet having a diameter smaller than the first width and greater than the second width toward the first region. In this case, the droplet is discharged such that the droplet lands at a position that faces a boundary line between the first region and the second region.
Public/Granted literature
- US20060045963A1 Method of forming wiring pattern and method of forming gate electrode for TFT Public/Granted day:2006-03-02
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