Invention Grant
US07678655B2 Spacer layer etch method providing enhanced microelectronic device performance
有权
间隔层蚀刻方法提供增强的微电子器件性能
- Patent Title: Spacer layer etch method providing enhanced microelectronic device performance
- Patent Title (中): 间隔层蚀刻方法提供增强的微电子器件性能
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Application No.: US11495348Application Date: 2006-07-28
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Publication No.: US07678655B2Publication Date: 2010-03-16
- Inventor: Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
- Applicant: Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.
Public/Granted literature
- US20080026518A1 Spacer layer etch method providing enhanced microelectronic device performance Public/Granted day:2008-01-31
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