A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.