Invention Grant
US07678679B2 Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method
失效
具有侧壁间隔件的垂直装置,形成侧壁间隔物的方法和场效应晶体管,以及图案化方法
- Patent Title: Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method
- Patent Title (中): 具有侧壁间隔件的垂直装置,形成侧壁间隔物的方法和场效应晶体管,以及图案化方法
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Application No.: US11414553Application Date: 2006-05-01
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Publication No.: US07678679B2Publication Date: 2010-03-16
- Inventor: Dirk Manger , Jyoti Gupta , Christoph Ludwig , Hans Lindemann
- Applicant: Dirk Manger , Jyoti Gupta , Christoph Ludwig , Hans Lindemann
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Edell, Shapiro & Finnan, LLC
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.
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