Invention Grant
- Patent Title: Exposure method for upper layer of hole of semiconductor device
- Patent Title (中): 半导体器件上层的曝光方法
-
Application No.: US11595917Application Date: 2006-11-13
-
Publication No.: US07678693B2Publication Date: 2010-03-16
- Inventor: Fumitoshi Sugimoto , Kiyoshi Ozawa
- Applicant: Fumitoshi Sugimoto , Kiyoshi Ozawa
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2006-164137 20060614
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove 11 just above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring groove 11A in a position spaced away from just above the hole is exposed to the light.
Public/Granted literature
- US20080032437A1 Exposure method for upper layer of hole of semiconductor device Public/Granted day:2008-02-07
Information query
IPC分类: