A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.