Invention Grant
US07679109B2 Semiconductor device, layout design method thereof, and layout design device using the same
有权
半导体器件，其布局设计方法以及使用其的布局设计器件
- Patent Title: Semiconductor device, layout design method thereof, and layout design device using the same
- Patent Title (中): 半导体器件，其布局设计方法以及使用其的布局设计器件
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Application No.: US11952176Application Date: 2007-12-07
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Publication No.: US07679109B2Publication Date: 2010-03-16
- Inventor: Yoshihiko Kato
- Applicant: Yoshihiko Kato
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2006-331915 20061208
- Main IPC: H01L23/50
- IPC: H01L23/50
Abstract:
A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circuit area being adjacent to the pad area in plan view; and a dummy pattern confined area for forbidding an arrangement of the dummy pattern in every layer included in the semiconductor device, the dummy pattern confined area being provided between the pad area and the input-output circuit area in plan view.
Public/Granted literature
- US20080135881A1 SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD THEREOF, AND LAYOUT DESIGN DEVICE USING THE SAME Public/Granted day:2008-06-12
Information query
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