Invention Grant
US07679118B2 Vertical transistor, memory cell, device, system and method of forming same
有权
垂直晶体管,存储单元,器件,系统及其形成方法
- Patent Title: Vertical transistor, memory cell, device, system and method of forming same
- Patent Title (中): 垂直晶体管,存储单元,器件,系统及其形成方法
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Application No.: US11151219Application Date: 2005-06-13
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Publication No.: US07679118B2Publication Date: 2010-03-16
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/94

Abstract:
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
Public/Granted literature
- US20060278910A1 Vertical transistor, memory cell, device, system and method of forming same Public/Granted day:2006-12-14
Information query
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