Invention Grant
- Patent Title: Bond pad design to minimize dielectric cracking
- Patent Title (中): 焊盘设计,以最小化电介质开裂
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Application No.: US11557372Application Date: 2006-11-07
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Publication No.: US07679180B2Publication Date: 2010-03-16
- Inventor: Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
- Applicant: Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Jeffrey M. Chamberlain
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H05K7/00 ; H01L21/44

Abstract:
An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.
Public/Granted literature
- US20080122100A1 NOVEL BOND PAD DESIGN TO MINIMIZE DIELECTRIC CRACKING Public/Granted day:2008-05-29
Information query
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