A delay time generation circuit is disclosed that includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of the last stage or a predetermined stage of the flip-flop circuits of the counter circuit. In the delay time generation circuit, a delay time is generated by the use of an output signal of one of the flip-flop circuits precedent to the last stage or the predetermined stage flip-flop circuit of the counter circuit at testing an electronic circuit. This configuration makes it possible to reduce the delay time without using a special high-speed clock.