Invention Grant
- Patent Title: Dual redundant dynamic logic
- Patent Title (中): 双冗余动态逻辑
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Application No.: US11269212Application Date: 2005-11-08
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Publication No.: US07679403B2Publication Date: 2010-03-16
- Inventor: David O. Erstad
- Applicant: David O. Erstad
- Applicant Address: US NJ Morristown
- Assignee: Honeywell International Inc.
- Current Assignee: Honeywell International Inc.
- Current Assignee Address: US NJ Morristown
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H03K19/096
- IPC: H03K19/096

Abstract:
A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.
Public/Granted literature
- US20070103194A1 Dual redundant dynamic logic Public/Granted day:2007-05-10
Information query
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