A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.