An image processing apparatus includes a decompression unit (302) that is configurable by dynamic reconfigurable logic into either a first decompression circuit (302a) or a second decompression circuit (302b) that has a slower decompression speed and a lower power consumption than the first decompression circuit (302a), a buffer unit (304) that temporarily stores image data decompressed by the decompression unit (302) to be supplied to an engine unit, and a detection unit (305) that detects a data amount accumulated in the buffer unit (304). In accordance with the data amount detected by the detection unit (305), the decompression unit (302) carries out reconfiguration into the first or second decompression circuit (302a/302b).