Invention Grant
- Patent Title: Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages
- Patent Title (中): 产生对应于多个阈值电压的电压的半导体存储器件
-
Application No.: US12276957Application Date: 2008-11-24
-
Publication No.: US07679959B2Publication Date: 2010-03-16
- Inventor: Noboru Shibata
- Applicant: Noboru Shibata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2005-168290 20050608
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04

Abstract:
A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section. A voltage generating circuit generates a voltage on the basis of the voltage data generated by the arithmetic circuit. The arithmetic circuit, when reading data from the memory cell at threshold level k (k
Public/Granted literature
- US20090073766A1 SEMICONDUCTOR MEMORY DEVICE WHICH GENERATES VOLTAGES CORRESPONDING TO A PLURALITY OF THRESHOLD VOLTAGES Public/Granted day:2009-03-19
Information query