Invention Grant
US07680968B2 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
有权
交换机/网络适配器端口包含可由直接执行逻辑元件和一个或多个密集逻辑设备以完全缓冲的双列直插存储器模块格式(FB-DIMM)选择性地访问的共享存储器资源,
- Patent Title: Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
- Patent Title (中): 交换机/网络适配器端口包含可由直接执行逻辑元件和一个或多个密集逻辑设备以完全缓冲的双列直插存储器模块格式(FB-DIMM)选择性地访问的共享存储器资源,
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Application No.: US11834439Application Date: 2007-08-06
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Publication No.: US07680968B2Publication Date: 2010-03-16
- Inventor: Lee A. Burton
- Applicant: Lee A. Burton
- Applicant Address: US CO Colorado Springs
- Assignee: SRC Computers, Inc.
- Current Assignee: SRC Computers, Inc.
- Current Assignee Address: US CO Colorado Springs
- Agency: Hogan & Hartson LLP
- Agent William J. Kubida; Michael C. Martensen
- Main IPC: G06F13/12
- IPC: G06F13/12

Abstract:
An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.
Public/Granted literature
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