Invention Grant
US07681016B2 Microprocessor instruction execution method for exploiting parallelism by time ordering operations in a single thread at compile time
失效
微处理器指令执行方法，用于在编译时通过单线程中的时间排序操作来利用并行性
- Patent Title: Microprocessor instruction execution method for exploiting parallelism by time ordering operations in a single thread at compile time
- Patent Title (中): 微处理器指令执行方法，用于在编译时通过单线程中的时间排序操作来利用并行性
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Application No.: US10518974Application Date: 2003-06-30
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Publication No.: US07681016B2Publication Date: 2010-03-16
- Inventor: Richard Michael Taylor
- Applicant: Richard Michael Taylor
- Applicant Address: GB Edinburgh
- Assignee: Critical Blue Ltd.
- Current Assignee: Critical Blue Ltd.
- Current Assignee Address: GB Edinburgh
- Agency: Saul Ewing LLP
- Priority: GB0215029.0 20020628
- International Application: PCT/GB03/02820 WO 20030630
- International Announcement: WO2004/003731 WO 20040108
- Main IPC: G06F9/00
- IPC: G06F9/00
Abstract:
A low overhead mechanism for supporting speculative execution and code compression in a Very Long Instruction Word (VLIW) microprocessor. Profitable speculations can be determined statically at compile time and a low overhead hardware recovery mechanism used that does not require compensation code.
Public/Granted literature
- US20050228976A1 Microprocessor instruction execution method for exploiting parallelism Public/Granted day:2005-10-13
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