Invention Grant
US07681098B2 Systems and methods for improved fault coverage of LBIST testing
失效
改进LBIST测试故障覆盖的系统和方法
- Patent Title: Systems and methods for improved fault coverage of LBIST testing
- Patent Title (中): 改进LBIST测试故障覆盖的系统和方法
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Application No.: US11379421Application Date: 2006-04-20
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Publication No.: US07681098B2Publication Date: 2010-03-16
- Inventor: Naoki Kiryu
- Applicant: Naoki Kiryu
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Law Offices of Mark L. Berrier
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) by determining weighting and/or seed values to be used in generating pseudorandom test bit patterns for each channel to optimize fault coverage. In one embodiment, a method includes generating a pseudorandom sequence of bits, applying a weighting value to the sequence, propagating the weighted sequence through one or more levels of logic, and capturing the resulting data. Metrics are then applied to the captured data to determine the suitability or optimality of the weighting value, and an optimal weighting value is selected. This may be performed for a plurality of trial values for each of a number of channels to obtain a set of weighting values for the different LBIST channels. The method may also include determining a seed value for the pseudorandom bit pattern generator.
Public/Granted literature
- US20070273401A1 Systems and Methods for Improved Fault Coverage of LBIST Testing Public/Granted day:2007-11-29
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