Invention Grant
- Patent Title: Chip scale package (CSP) assembly apparatus and method
- Patent Title (中): 芯片级封装（CSP）组装装置及方法
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Application No.: US11483861Application Date: 2006-07-10
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Publication No.: US07682874B2Publication Date: 2010-03-23
- Inventor: Tan Xiaochun , Li Yunfang
- Applicant: Tan Xiaochun , Li Yunfang
- Applicant Address: CN
- Assignee: Shanghai KaiHong Technology Co., Ltd.
- Current Assignee: Shanghai KaiHong Technology Co., Ltd.
- Current Assignee Address: CN
- Agency: Fountainhead Law Group PC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/44
Abstract:
In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.
Public/Granted literature
- US20080014677A1 Chip scale package (CSP) assembly apparatus and method Public/Granted day:2008-01-17
Information query
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