Invention Grant
US07682880B2 Method and device for producing layout patterns of a semiconductor device having an even wafer surface
失效
用于制造具有均匀晶片表面的半导体器件的布局图案的方法和装置
- Patent Title: Method and device for producing layout patterns of a semiconductor device having an even wafer surface
- Patent Title (中): 用于制造具有均匀晶片表面的半导体器件的布局图案的方法和装置
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Application No.: US11717730Application Date: 2007-03-14
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Publication No.: US07682880B2Publication Date: 2010-03-23
- Inventor: Hidekazu Kawashima , Tetsuya Katoh
- Applicant: Hidekazu Kawashima , Tetsuya Katoh
- Applicant Address: JP Kawasaki, Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kawasaki, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2003-005505 20030114
- Main IPC: H01L21/82
- IPC: H01L21/82 ; G06F17/50
Abstract:
Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.
Public/Granted literature
- US20070155061A1 Method and device for producing layout patterns of a semiconductor device having an even wafer surface Public/Granted day:2007-07-05
Information query
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