Invention Grant
US07682885B2 Method for fabricating vertical channel transistor in a semiconductor device
失效
在半导体器件中制造垂直沟道晶体管的方法
- Patent Title: Method for fabricating vertical channel transistor in a semiconductor device
- Patent Title (中): 在半导体器件中制造垂直沟道晶体管的方法
-
Application No.: US12164867Application Date: 2008-06-30
-
Publication No.: US07682885B2Publication Date: 2010-03-23
- Inventor: Jun-Hee Cho , Sang-Hoon Park
- Applicant: Jun-Hee Cho , Sang-Hoon Park
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: Lowe Hauptman Ham & Berner LLP
- Priority: KR10-2007-0135187 20071221
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L21/00

Abstract:
A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
Public/Granted literature
- US20090163000A1 METHOD FOR FABRICATING VERTICAL CHANNEL TRANSISTOR IN A SEMICONDUCTOR DEVICE Public/Granted day:2009-06-25
Information query
IPC分类: