Invention Grant
- Patent Title: Self aligned narrow storage elements for advanced memory device
- Patent Title (中): 自对准窄存储元件,用于高级存储器件
-
Application No.: US11746122Application Date: 2007-05-09
-
Publication No.: US07682905B2Publication Date: 2010-03-23
- Inventor: Suketu Arun Parikh
- Applicant: Suketu Arun Parikh
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Turocy & Watson, LLP
- Main IPC: H01L21/8247
- IPC: H01L21/8247

Abstract:
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
Public/Granted literature
- US20080280410A1 SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE Public/Granted day:2008-11-13
Information query