A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried n+-doped regions (31) for the PMOS varactor and the npn transistor in a p-doped substrate (10, 41); (ii) simultaneously forming n-doped wells (41) above the buried n+-doped regions (31); (iii) simultaneously forming field isolation areas (81) around the n-doped regions (41); (iv) forming a PMOS gate region (111, 194) and a p-doped base each in a respective one of the n-doped wells (41); and (v) simultaneously forming n+-doped contacts to the buried n+-doped regions (31); the contacts being separated from the n-doped wells (41). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n+-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).