Invention Grant
- Patent Title: Method of forming isolation layer of semiconductor device
- Patent Title (中): 形成半导体器件隔离层的方法
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Application No.: US11642546Application Date: 2006-12-21
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Publication No.: US07682928B2Publication Date: 2010-03-23
- Inventor: Myung Il Kang
- Applicant: Myung Il Kang
- Applicant Address: KR Seoul
- Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee: Dongbu Electronics Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Lowe Hauptman Ham & Berner, LLP
- Priority: KR10-2005-0131498 20051228
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer. In accordance with an embodiment of the present invention, an isolation layer is completed by: forming a buffer insulating layer on a silicon substrate and patterning the buffer insulating layer; selectively etching the silicon substrate and forming trenches including a relatively big region and a relatively narrow region; depositing a first insulating layer and a second insulating layer sequentially on a whole surface of the silicon substrate; selectively removing the second insulating layer and forming a chemical mechanical polishing (CMP) stop layer only on the relatively large trench region; planarizing the first insulating layer using the CMP stop layer; and removing all of the CMP stop layer and the buffer insulating layer and completing an isolation layer.
Public/Granted literature
- US20070148907A1 Method of forming isolation layer of semiconductor device Public/Granted day:2007-06-28
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