An integrated circuit having a memory cell and/or memory cell array including a plurality of memory cells (as well as techniques for reading, controlling and/or operating, the memory cell, and/or memory cell array). Each memory cell includes at least one transistor having an electrically floating body transistor and an active access element. The electrically floating body region of the transistor forms a storage area or node of the memory cell wherein an electrical charge which is representative of a data state is stored in the electrically floating body region. The active access element is coupled to the electrically floating body transistor to facilitate programming of the memory cell and to provide a relatively large amount of majority carriers to the storage area or node of the memory cell during a write operation. The memory cell and/or memory cell array of the present inventions may be incorporated in an integrated circuit device, for example, a logic device (such as, for example, a microcontroller or microprocessor) or may comprise a portion of a memory device (such as, for example, a discrete memory).