Invention Grant
- Patent Title: MOS devices with multi-layer gate stack
- Patent Title (中): 具有多层门极堆叠的MOS器件
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Application No.: US12347061Application Date: 2008-12-31
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Publication No.: US07683443B2Publication Date: 2010-03-23
- Inventor: Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
- Applicant: Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia, Fisher & Lorenz, P.C.
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
Public/Granted literature
- US20090115001A1 MOS DEVICES WITH MULTI-LAYER GATE STACK Public/Granted day:2009-05-07
Information query
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