A chip packaging overflow proof device includes a chip disposed on a substrate; a circuit connected to the chip being provided to each of both sides of the substrate; both of the substrate and the chip being placed in a packaging base; a socket being each provided on both sides of the packaging base to receive insertion by a lid; a first cable-terminating hole being provided between the socket and the lid to permit the circuit to penetrate through; one or a plurality of retaining wall being disposed on the packaging base at where closer to the socket; a second cable-terminating hole being provided on the retaining hole; an overflow space being defined between the retaining wall and the socket; the overflow space being disposed at a level lower than that of the second cable-terminating hole; and the overflow space accepts any squeeze-out from a chip packaging colloid.