Invention Grant
- Patent Title: Electronic component unit
- Patent Title (中): 电子元件单元
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Application No.: US11527461Application Date: 2006-09-27
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Publication No.: US07683482B2Publication Date: 2010-03-23
- Inventor: Kazuto Nishida , Hidenobu Nishikawa , Yoshinori Wada , Hiroyuki Otani
- Applicant: Kazuto Nishida , Hidenobu Nishikawa , Yoshinori Wada , Hiroyuki Otani
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP11-21800 19990129; JP11-22015 19990129
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44 ; H05K3/32
Abstract:
A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.
Public/Granted literature
- US20070013067A1 Electronic component mounting method and apparatus Public/Granted day:2007-01-18
Information query
IPC分类:
