Invention Grant
- Patent Title: Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance
- Patent Title (中): 用于最小化寄生电阻的电子设备互连路由和互连路由方法
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Application No.: US11302007Application Date: 2005-12-09
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Publication No.: US07683486B2Publication Date: 2010-03-23
- Inventor: Suman K. Banerjee , Alain C. Duvallet , Craig Jasper , Olin L. Hartin , Walter Parmon
- Applicant: Suman K. Banerjee , Alain C. Duvallet , Craig Jasper , Olin L. Hartin , Walter Parmon
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia, Fisher & Lorenz, P.C.
- Main IPC: H01L29/40
- IPC: H01L29/40
Abstract:
Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
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