Invention Grant
- Patent Title: T-switch buffer, in particular for FPGA architectures
- Patent Title (中): T开关缓冲器,特别适用于FPGA架构
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Application No.: US11810792Application Date: 2007-06-06
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Publication No.: US07683674B2Publication Date: 2010-03-23
- Inventor: Luca Ciccarelli , Andrea Lodi
- Applicant: Luca Ciccarelli , Andrea Lodi
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics, S.r.l.
- Current Assignee: STMicroelectronics, S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Graybeal Jackson LLP
- Agent Lisa K. Jorgenson; Kevin D. Joblonski
- Priority: EP06011668 20060606
- Main IPC: H03K19/094
- IPC: H03K19/094

Abstract:
An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.
Public/Granted literature
- US20070279088A1 T-switch buffer, in particular for FPGA architectures Public/Granted day:2007-12-06
Information query
IPC分类: