Invention Grant
US07683674B2 T-switch buffer, in particular for FPGA architectures 有权
T开关缓冲器,特别适用于FPGA架构

T-switch buffer, in particular for FPGA architectures
Abstract:
An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.
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