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US07683679B2 AFSM circuit and method for low jitter PLL CMOS programmable divider 有权
AFSM电路和低抖动PLL CMOS可编程分频器的方法

AFSM circuit and method for low jitter PLL CMOS programmable divider
Abstract:
A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1,F2,F3) each of which is a divided-down representation of the input clock signal (CLK) and each of which is phase-shifted by a predetermined amount with respect to another of the phase signals (F0,F1,F2,F3). Programmable circuitry (22) operates in response to both dynamic divide ratio information (DIV_RATIO) and the information representative of the plurality of phase signals (F0,F1,F2,F3) so as to generate an output clock signal (CLKOUT) that is divided down according to both the dynamic divide ratio information and the information representative of the plurality of phase signals (F0,F1,F2,F3).
Abstract(Chinese):

分频器（10A）包括被配置为计数器（20）的异步有限状态机（AFSM），其具有耦合到输入时钟信号（CLK）的输入，用于产生表示多个相位信号（F0，F1，F2 ，F3），其中的每一个是输入时钟信号（CLK）的分频表示，并且每个相对于另一个相位信号（F0，F1，F2，F3）相移一个预定量。 可编程电路（22）响应于动态分频比信息（DIV_RATIO）和表示多个相位信号（F0，F1，F2，F3）的信息而工作，以便产生分频的输出时钟信号（CLKOUT） 根据动态分频比信息和表示多个相位信号（F0，F1，F2，F3）的信息，下降。

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