Invention Grant
- Patent Title: System and method for implementing a digital phase-locked loop
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Application No.: US12012677Application Date: 2008-02-05
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Publication No.: US07683685B2Publication Date: 2010-03-23
- Inventor: Bernard J. Griffiths
- Applicant: Bernard J. Griffiths
- Applicant Address: JP Tokyo US NJ Park Ridge
- Assignee: Sony Corporation,Sony Electronics Inc.
- Current Assignee: Sony Corporation,Sony Electronics Inc.
- Current Assignee Address: JP Tokyo US NJ Park Ridge
- Agency: Redwood Patent Law
- Agent Gregory J. Koerner
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter.
Public/Granted literature
- US20090195276A1 System and method for implementing a digital phase-locked loop Public/Granted day:2009-08-06
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