Invention Grant
- Patent Title: Circuitry and method for buffering a power mode control signal
- Patent Title (中): 用于缓冲功率模式控制信号的电路和方法
-
Application No.: US12130590Application Date: 2008-05-30
-
Publication No.: US07683697B2Publication Date: 2010-03-23
- Inventor: Matthew S. Berzins , Charles A. Cornell , Andrew P. Hoover
- Applicant: Matthew S. Berzins , Charles A. Cornell , Andrew P. Hoover
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; Robert L. King
- Main IPC: H03K3/01
- IPC: H03K3/01

Abstract:
A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.
Public/Granted literature
- US20090295467A1 CIRCUITRY AND METHOD FOR BUFFERING A POWER MODE CONTROL SIGNAL Public/Granted day:2009-12-03
Information query