Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US10585779Application Date: 2004-12-29
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Publication No.: US07683721B2Publication Date: 2010-03-23
- Inventor: Johannes Petrus Maria Van Lammeren , Jozef Jacobus Agnes Maria Verlinden , Edwin Jan Schapendonk
- Applicant: Johannes Petrus Maria Van Lammeren , Jozef Jacobus Agnes Maria Verlinden , Edwin Jan Schapendonk
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP04100072 20040112
- International Application: PCT/IB2004/052931 WO 20041229
- International Announcement: WO2005/069489 WO 20050728
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
The present invention relates to a phase locked loop arrangement having an oscillator circuit (240) controlled in response to an output signal of a phase or frequency detection circuit (210), wherein change control (130) are provided for generating a blocking signal in response to the outputs of a first timer (110) to which a predetermined threshold frequency is supplied and a second timer (112) to which an output frequency of the oscillator circuit (240) is supplied. Based on the blocking signal, blocking (260) suppress supply of the output signal to said oscillator circuit (240). Thereby, the output frequency of the PLL arrangement can be prevented from changing beyond the frequency threshold, while only one PLL circuit is required.
Public/Granted literature
- US20090189698A1 Pll circuit Public/Granted day:2009-07-30
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