Invention Grant
- Patent Title: Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems
- Patent Title (中): 锁相环电路,偏移PLL发射机,射频集成电路和手机系统
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Application No.: US11865729Application Date: 2007-10-02
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Publication No.: US07683723B2Publication Date: 2010-03-23
- Inventor: Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
- Applicant: Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2005-094161 20050329; JP2005-326340 20051110
- Main IPC: H03L7/07
- IPC: H03L7/07 ; H03L7/085

Abstract:
A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
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