Invention Grant
- Patent Title: Reducing read failure in a memory device
- Patent Title (中): 减少存储设备中的读取失败
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Application No.: US11513891Application Date: 2006-08-31
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Publication No.: US07684243B2Publication Date: 2010-03-23
- Inventor: Seiichi Aritome , Alessandro Torsi , Carlo Musilli
- Applicant: Seiichi Aritome , Alessandro Torsi , Carlo Musilli
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04

Abstract:
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
Public/Granted literature
- US20080056008A1 Reducing read failure in a memory device Public/Granted day:2008-03-06
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