Invention Grant
- Patent Title: Non-volatile memory array architecture with joined word lines
- Patent Title (中): 具有连接字线的非易失性存储器阵列架构
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Application No.: US11928086Application Date: 2007-10-30
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Publication No.: US07684245B2Publication Date: 2010-03-23
- Inventor: Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
- Applicant: Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
- Applicant Address: US CA San Jose
- Assignee: Atmel Corporation
- Current Assignee: Atmel Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; G11C5/06

Abstract:
In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
Public/Granted literature
- US20090109754A1 NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES Public/Granted day:2009-04-30
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