Invention Grant
US07684532B2 Clock data recovery circuitry associated with programmable logic device circuitry
有权
与可编程逻辑器件电路相关的时钟数据恢复电路
- Patent Title: Clock data recovery circuitry associated with programmable logic device circuitry
- Patent Title (中): 与可编程逻辑器件电路相关的时钟数据恢复电路
-
Application No.: US11796136Application Date: 2007-04-25
-
Publication No.: US07684532B2Publication Date: 2010-03-23
- Inventor: Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
- Applicant: Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Main IPC: H04L7/00
- IPC: H04L7/00
Abstract:
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
Public/Granted literature
- US20080031385A1 Clock data recovery circuitry associated with programmable logic device circuitry Public/Granted day:2008-02-07
Information query
