Invention Grant
US07687303B1 Method for determining via/contact pattern density effect in via/contact etch rate
有权
确定通孔/接触蚀刻速率的通孔/接触图案密度效应的方法
- Patent Title: Method for determining via/contact pattern density effect in via/contact etch rate
- Patent Title (中): 确定通孔/接触蚀刻速率的通孔/接触图案密度效应的方法
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Application No.: US11264930Application Date: 2005-11-01
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Publication No.: US07687303B1Publication Date: 2010-03-30
- Inventor: Valeriy Sukharev , Ara Markosian
- Applicant: Valeriy Sukharev , Ara Markosian
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.
Information query
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