Invention Grant
US07687361B2 Method of fabricating a transistor having a triple channel in a memory device
有权
在存储器件中制造具有三通道的晶体管的方法
- Patent Title: Method of fabricating a transistor having a triple channel in a memory device
- Patent Title (中): 在存储器件中制造具有三通道的晶体管的方法
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Application No.: US11155833Application Date: 2005-06-17
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Publication No.: US07687361B2Publication Date: 2010-03-30
- Inventor: Se Aug Jang , Yong Soo Kim , Jae Geun Oh
- Applicant: Se Aug Jang , Yong Soo Kim , Jae Geun Oh
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2005-0036794 20050502
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.
Public/Granted literature
- US20060246671A1 Method of fabricating a transistor having a triple channel in a memory device Public/Granted day:2006-11-02
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