Invention Grant
- Patent Title: Method of forming a semiconductor isolation trench
- Patent Title (中): 形成半导体隔离沟槽的方法
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Application No.: US11342102Application Date: 2006-01-27
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Publication No.: US07687370B2Publication Date: 2010-03-30
- Inventor: Toni D. Van Gompel , John J. Hackenberg , Rode R. Mora , Suresh Venkatesan
- Applicant: Toni D. Van Gompel , John J. Hackenberg , Rode R. Mora , Suresh Venkatesan
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Robert L. King; Ranjeev Singh
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/311 ; H01L21/302

Abstract:
A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.
Public/Granted literature
- US20070178661A1 Method of forming a semiconductor isolation trench Public/Granted day:2007-08-02
Information query
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