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US07687407B2 Method for reducing line edge roughness for conductive features 有权
降低导线特征线边缘粗糙度的方法

Method for reducing line edge roughness for conductive features
Abstract:
The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (θ1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ2).
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