Invention Grant
- Patent Title: Method for reducing line edge roughness for conductive features
- Patent Title (中): 降低导线特征线边缘粗糙度的方法
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Application No.: US11070593Application Date: 2005-03-02
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Publication No.: US07687407B2Publication Date: 2010-03-30
- Inventor: David G. Farber , Brian E. Goodllin , Robert Kraft
- Applicant: David G. Farber , Brian E. Goodllin , Robert Kraft
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (θ1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ2).
Public/Granted literature
- US20060121739A1 Method for reducing line edge roughness for conductive features Public/Granted day:2006-06-08
Information query
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