Invention Grant
US07687834B2 Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
失效
在硅和硅合金中使用互补结场效应晶体管和MOS晶体管的集成电路
- Patent Title: Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
- Patent Title (中): 在硅和硅合金中使用互补结场效应晶体管和MOS晶体管的集成电路
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Application No.: US12263854Application Date: 2008-11-03
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Publication No.: US07687834B2Publication Date: 2010-03-30
- Inventor: Ashok K. Kapoor
- Applicant: Ashok K. Kapoor
- Applicant Address: US CA Los Gatos
- Assignee: SuVolta, Inc.
- Current Assignee: SuVolta, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Baker Botts L.L.P.
- Main IPC: H01L29/80
- IPC: H01L29/80 ; H01L21/20
Abstract:
This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
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