Invention Grant
- Patent Title: Memory utilizing oxide-conductor nanolaminates
- Patent Title (中): 记忆利用氧化物导体的Nanolaminates
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Application No.: US11496196Application Date: 2006-07-31
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Publication No.: US07687848B2Publication Date: 2010-03-30
- Inventor: Leonard Forbes , Kie Y. Ahn
- Applicant: Leonard Forbes , Kie Y. Ahn
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.
Public/Granted literature
- US20090218612A1 MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES Public/Granted day:2009-09-03
Information query
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