Invention Grant
- Patent Title: Method for manufacturing semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US12128796Application Date: 2008-05-29
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Publication No.: US07687849B2Publication Date: 2010-03-30
- Inventor: Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
- Applicant: Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2001-253028 20010823
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
Public/Granted literature
- US20080237752A1 METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2008-10-02
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