Invention Grant
- Patent Title: Semiconductor device with reduced parasitic inductance
- Patent Title (中): 降低寄生电感的半导体器件
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Application No.: US11809023Application Date: 2007-05-30
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Publication No.: US07687885B2Publication Date: 2010-03-30
- Inventor: Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- Applicant: Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Townsend and Townsend and Crew LLP
- Priority: JP2006-149489 20060530
- Main IPC: H01L31/111
- IPC: H01L31/111 ; G05F1/10 ; H02J3/12 ; H01L25/04 ; H01L25/18 ; G06F1/26 ; H02M3/155
Abstract:
The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
Public/Granted literature
- US20070278516A1 Semiconductor device and power source unit using the same Public/Granted day:2007-12-06
Information query
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