Invention Grant
US07688083B2 Analogue measurement of alignment between layers of a semiconductor device 有权
模拟测量半导体器件的层之间的对准

  • Patent Title: Analogue measurement of alignment between layers of a semiconductor device
  • Patent Title (中): 模拟测量半导体器件的层之间的对准
  • Application No.: US11575863
    Application Date: 2005-09-19
  • Publication No.: US07688083B2
    Publication Date: 2010-03-30
  • Inventor: Dirk Kenneth De VriesAlbert Van De Goor
  • Applicant: Dirk Kenneth De VriesAlbert Van De Goor
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP04300618 20040923
  • International Application: PCT/IB2005/053073 WO 20050919
  • International Announcement: WO2006/033073 WO 20060330
  • Main IPC: G01R27/08
  • IPC: G01R27/08 G01R31/28
Analogue measurement of alignment between layers of a semiconductor device
Abstract:
A method of obtaining parametric test data for use in monitoring alignment between layers of a semiconductor device. The method employs a test structure comprising a meander (10, 30) of the material of a first layer of the semiconductor device, deposited relative to a conductive line (18,38). A number of sets (16a, 16b, 16e, 16d) of components 16, such as contacts or vias, are provided relative to the meander (10), at successively smaller distances therefrom. A single analogue measurement can be performed between a first and (A) of the meander (10, 30) and the conductive line (18, 38) so as to determine the resistance therebetween, and the critical distance at (or on acceptable margin in relation thereto) between the first layer and a component of the semiconductor device can be obtained.
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