Invention Grant
US07688240B2 Method and apparatus for calibrating an RDAC for end-to-end tolerance correction of output resistance
有权
校准RDAC的输出电阻的端到端容限校正的方法和装置
- Patent Title: Method and apparatus for calibrating an RDAC for end-to-end tolerance correction of output resistance
- Patent Title (中): 校准RDAC的输出电阻的端到端容限校正的方法和装置
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Application No.: US12113946Application Date: 2008-05-02
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Publication No.: US07688240B2Publication Date: 2010-03-30
- Inventor: Dinesh Jain , Kaushal Kumar Jha
- Applicant: Dinesh Jain , Kaushal Kumar Jha
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Kenyon & Kenyon LLP
- Main IPC: H03M1/10
- IPC: H03M1/10

Abstract:
A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.
Public/Granted literature
- US20090273497A1 METHOD AND APPARATUS FOR CALIBRATING AN RDAC FOR END-TO-END TOLERANCE CORRECTION OF OUTPUT RESISTANCE Public/Granted day:2009-11-05
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