Invention Grant
US07688658B2 Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof 有权
其中安装有多个存储器宏的半导体器件及其测试方法

  • Patent Title: Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof
  • Patent Title (中): 其中安装有多个存储器宏的半导体器件及其测试方法
  • Application No.: US12102561
    Application Date: 2008-04-14
  • Publication No.: US07688658B2
    Publication Date: 2010-03-30
  • Inventor: Naoki Yamada
  • Applicant: Naoki Yamada
  • Applicant Address: JP Osaka
  • Assignee: Panasonic Corporation
  • Current Assignee: Panasonic Corporation
  • Current Assignee Address: JP Osaka
  • Agency: Steptoe & Johnson LLP
  • Priority: JP2007-109937 20070419
  • Main IPC: G11C7/00
  • IPC: G11C7/00
Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof
Abstract:
According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.
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