Invention Grant
- Patent Title: Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof
- Patent Title (中): 其中安装有多个存储器宏的半导体器件及其测试方法
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Application No.: US12102561Application Date: 2008-04-14
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Publication No.: US07688658B2Publication Date: 2010-03-30
- Inventor: Naoki Yamada
- Applicant: Naoki Yamada
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Steptoe & Johnson LLP
- Priority: JP2007-109937 20070419
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.
Public/Granted literature
- US20080259704A1 SEMICONDUCTOR DEVICE IN WHICH A PLURALITY OF MEMORY MACROS ARE MOUNTED, AND TESTING METHOD THEREOF Public/Granted day:2008-10-23
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